Von Neumann vs Harvard Architectures | Computer Architectures Course
OPIT - Open Institute of Technology
https://www.youtube.com/watch?v=quoO7d27dUA

Transkript (automatisch erstellt)

0:05 hi everyone in this session we're going to go a little abstract we're going to look at the Von Newman the Harvard and the modified Harvard
0:14 architectures and we'll go through each of these three in order so Von Newman first then we'll look at the Harvard uh and then we'll look at the uh modified
0:22 Harvard architectures first off the V Newman so it's been around for quite a long time it was introduced by a fellow John Von
0:30 Newman in 1945 so before I was born and it consists of a control unit the ALU or arithmetic logic unit a
0:41 register set and then also a region for memory and then of course the ability to uh interact with input output devices so the memory region contains program
0:51 instructions uh and also the data and it has a single memory area for program instructions and for the data so it's only one m memory
1:01 location and here's a visual representation of the Von Numan architecture so this particular architecture is easy for circuit
1:10 designers all the code and data is in a single memory region we can see down here so we have one memory region simple but there are some issues as we'll see
1:19 uh the main issue is with this single memory space so this area down here so you can see here are three components of the processor right the control unit the
1:28 registers and our uh arithmetic logic unit or Al so the issue here with the memory is uh there's two things there's the fact
1:37 that it's a perform it can be a performance bottleneck and also that there are issues with security and we'll take a
1:43 look at each of these two issues uh momentarily excuse me first off the bottleneck so the single memory space requires multiple
1:53 memory Cycles uh for instruction and for data access so that can be an issue uh most most programs work with data stored in memory allocated separately uh from
2:04 program instructions now we can use cache memory and this has become a big part of modern processor Design This is this idea of
2:11 cache and we're going to talk quite a bit about this a little bit further on in the course so the shared communication path
2:18 to the processor is still the main issue so all of this all of these all of the data and and all of the instructions uh buying for the same path to the to the
2:29 processor so that's a bottleneck issue the other is security so because the information is shared for program and data basically
2:39 malicious coders can store code as data right and that can be an issue because then that uh data can actually be run as code and do uh malicious things so we
2:52 can use this da data uh and ask the processor to execute it it being self-modifying code and can do malicious things for
3:03 example manipulate or delete other pieces of data uh and the buffer overflow is a common flaw and this can be exploited
3:13 and was exploited in early processor design so a hacker overflows the buffer then rewrites the program's return address so because the buffer was
3:21 overflowing we rewrite where the program comes back to and it comes back to an area of malicious code for example and that code is then executed so it points
3:30 to the malicious code rather than the original program and so now basically uh the hacker can run any code that they want um for example access um
3:43 information or data that they shouldn't otherwise have access to so that can be an issue moving on to the Harvard
3:51 architecture originally implemented around the same time one year earlier in 1944 as the Harvard Mark 1 and it had one address space and a
4:01 memory bus uh for program instructions and a separate address space and memory bus for data so separating uh program instructions from
4:11 data so the benefit of this is simultaneous access to instructions and also to data but the one issue is is that it
4:19 doubles the instructions uh needed for the processor here's the uh Harvard architecture here and you can see the
4:26 difference of course uh we at the center we still have our CPU with our three components our control unit our registers and our arithmetic logic unit
4:36 we still have our input output devices of course this varies depending on the type of system that's actually um constructed and then here we have our
4:45 instruction memory this is the the main difference our instruction memory uh and our data memory so they're separate so that's the kind of the main difference
4:52 between the bond Newan architecture and the Harvard architecture the modified Harvard architecture Ure uh several variants of
5:01 this um they're used in modern computer design so a little bit of both uh collectively called the modified uh Harvard architecture and generally
5:10 there's some degree of separation between programs and data so we want to optimize as best we can with some separation but typically some means of
5:17 storing data also in program memory so that the uh processor doesn't have to do quite as much as it would with a standard Harvard
5:27 architecture and less commonly uh the reverse so also um some means of storing um uh the other way so storing program memory and data uh storing programs in
5:39 data memory so a little bit of Vice Versa but less commonly the other way here's what the modern uh Harvard architecture looks like so the the the
5:48 former not the latter where we have uh our instruction memory and we also have a little bit of data memory in there with that instruction memory again just
5:55 to optimize uh processor usage other than that it's pretty much the same as the Harvard architecture and this is what's used in many uh real world
6:04 computer systems today now Digital Signal processors or dsps achieve benefits uh from this type
6:14 of architecture so they can execute one multiple accumulate or one Mac it's called operation per uh processor clock cycle and typically instruction memory
6:24 is readon so requires uh constant data values only and that's really all I wanted to talk about today we're going to go a lot more
6:32 into cache memory and the different levels of cach memory uh a little bit forward on in this course and just to summarize then we
6:40 talked about three things we talked about the uh Von Newan architecture which has one memory space then we talked about the Harvard architecture
6:48 which has two memory spaces one for data and one for instructions and then the modified Harvard architecture which allows a little bit of data to be stored
6:58 in the instruction memory just to op more optimize uh processor usage and most modern architectures use the modified hard Harvard AR architecture
7:08 all right so thanks for tuning in and we'll see you again in the next session take care