Harvard Architecture versus Von Neumann Architecture
Computer Science Lessons
https://www.youtube.com/watch?v=4nY7mNHLrLk

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0:00 the Harvard architecture is named after IBM's so-called Harvard Mark 1 a computer that helped to develop the atomic bomb during World War II in the
0:10 Harvard Mark 1 instructions were stored on punched paper tape and data were stored in electromechanical counters within the
0:19 CPU the principle of storing instructions and data in different places became known as the Harvard architecture before we look at the
0:28 Harvard architecture let's first consider a traditional single core computer in which the programs and the data are both stored in the main memory
0:38 the ram this is known as the vuman architecture to fetch a program instruction or a data item into the CPU for processing the relevant memory
0:49 address is first sent to the main memory via the address bus then an instruction or a data item is sent back to the CPU via the datab bus
1:00 saving a data item in the memory also requires that a memory address is sent to the memory via the address bus then the data is conveyed from the CPU to the
1:11 memory via the data bus notice that memory addresses only ever travel in One Direction but data can travel both ways the fact that program instructions and
1:22 data share the same memory and the same buses that connect the CPU to the memory means that they have to be fetched separately an instruction to load a data
1:34 item from the memory into the CPU for example will need two fetch execute Cycles to complete one for the instruction and one for the
1:43 data this is known as the Von Newman bottleneck the Harvard architecture improves on this by storing instructions
1:54 and data in separate memories and because these memories are separate they don't need to be built in the same way for example depending on the application
2:04 there could be more instruction memory than data memory this would require a wider address bus for the instruction
2:12 memory furthermore the instruction memory might have a bigger word width that is each location in the instruction memory could be capable of storing more
2:21 bits than a location in the data memory consequently the instruction bus would be wider than the data bus depending on the application it might
2:32 also be appropriate to use readon memory for the instructions but read write memory for the data the Harvard architecture is most
2:41 often found in digital signal processes soall DSP applications include purpose-built hardware for audio and video processing Medical Imaging
2:53 applications such as x-ray MRI and CAT scans fitness trackers and smart watches and digital assistants such as Amazon's Alexa and Google home what these DSP
3:07 applications have in common is the capture and digitization of analog information followed by some form of processing of the digital signal
3:17 generated for example a speech processing application might digitize a spoken instruction then filter out any interference or background noise before
3:26 passing it on to an AI to be interpreted and even a modern personal computer borrows design principles from the Harvard
3:37 architecture a typical CPU has several cores each with its own arithmetic and logic unit and their operation is managed by a single control
3:47 unit it also contains multiple levels of cache memory cach memory temporarily stores frequently used instructions and data
3:57 rather than having to make multiple requests to the ram each core has its own level one cache Which is closest to the core meaning it can be accessed very
4:08 quickly each core also has its own level two cache which is larger than the level one cache but a little slower to access the level three cache is shared
4:18 by all of the cores it has the biggest capacity but operates more slowly than the other two levels nevertheless all of the CPU cache
4:28 memory is much faster than the main memory because there's no need for the instructions and data in the cache to travel along the data
4:37 bus each level one cache is split in two some of it for instructions and some of it for data this is sometimes referred to as the modified Harvard architecture
4:51 the main benefit of this approach of course is that data and instructions can be fetched and processed simultaneously by the same
5:01 core so as you've seen the original design principle of the Harvard Mark 1 that is different memories for instructions and data is still relevant
5:13 today